(a) Field of the Invention
This invention relates to a clock signal reproducing circuit for a player reproducing information of a disc such as a digital audio disc or a video disc capable of reproducing, from a signal reproduced from the disc via a pickup head, a clock signal which was used for setting a timewise reference in recording information pits on the disc and, more particularly, to a clock signal reproducing circuit capable of accurately performing phase error detection in controlling a phase relation between the reproduced clock signal and the signal reproduced from the disc and also performing the control of the phase relation accurately and easily thereby to reproduce an accurate clock signal.
(b) Description of the Prior Art
In a player for reproducing information of a disc, a clock signal which is reproduced from a signal reproduced from the disc via pickup head and representing an information pit on the disc (hereinafter referred to as "reproduced signal") is utilized for rotation control in a CLV (constant linear velocity) system or signal demodulation.
FIG. 1 shows a general structure of an overall control system for an optical type digital audio disc reproducing player. In this figure, a disc 1 is placed on a turntable 2 and driven by a spin motor 3. An optical type pickup head 4 contains a semiconductor laser, an optical system, a light-receiving element, a focus control coil 5 and a tracking control coil 6. The pickup head 4 projects a laser beam from an objective lens 7 onto the recording surface of the disc 1 and receives the reflected beam through the objective lens 7. The pickup head 4 is fed in the radial direction of the disc 1 by means of a feed motor 8.
A signal which has been detected by the pickup head 4 is supplied to a demodulation circuit 12 through a pre-amplifier 9, an AGC (automatic gain control) circuit 10 and a waveform shaping circuit 11.
A focus servo circuit 13 detects out-of-focusing of the laser beam in response to a light receiving signal and actuates the focus control coil 5 so that the laser beam is accurately focused on the recording surface of the disc.
A tracking error detecting circuit 15 detects, responsive to an information pit reproduction signal, deviation of the laser beam from the pit train and a tracking servo circuit 14 thereupon actuates the tracking control coil 6 to correct the error. In a case where the deviation in the tracking has enlarged with the progress of reproduction of the disc to such a degree that the tracking control coil 6 can no longer correct the deviation, a tracking deviation detecting circuit 24 delivers out a feed request signal so that the feed motor 8 is driven by a feed motor driving circuit 40 through a system control circuit 37.
The output signal of the waveform shaping circuit 11 is not only supplied to the demodulation circuit 12 but also utilized for preparation of a detection signal in the CLV (constant linear velocity) disc rotation servo. More specifically, the output signal of the waveform shaping circuit 11 is applied to a clock signal reproducing circuit 16 where a clock signal is reproduced. A synchronizing signal detecting circuit 17 detects and delivers out a synchronizing signal contained in the output signal of the waveform shaping circuit 11. The synchronizing signal delivered from the synchronizing signal detecting circuit 17 is divided in frequency by a frequency divider circuit 18 and thereafter is applied to a phase comparator circuit 19. The phase comparator circuit 19 compares the frequency divided signal with a signal obtained by frequency-dividing by a frequency divider circuit 21 a master clock pulse generated from a master clock oscillator circuit 20 and controls the spin motor 3 through a disc rotation servo circuit 22 so that these signals are brought in phase with each other.
The demodulation circuit 12 demodulates the signal which was recorded on the disc 1 after being modulated by EFM (eight to fourteen modulation) to the original 8-bit signal and also removes signals such as coupling bits and a synchronizing signal which have now become unnecessary. A data control circuit 26, an error correction circuit 27 and a memory circuit 28 serve to deinterleave an output signal of the demodulation circuit 12 which was recorded on the disc 1 after being interleaved to the original signal, check whether there is an error involved in the signal, effect error correction in the error correction circuit 27 if there is an error and effect error interpolation if the error is too large to be corrected. Further, data alignment and absorption of wow and flutter are performed by storing the signal after the error correction or interpolation in the memory circuit 28 at a timing of the reproduced clock signal and thereafter reading out this signal at a timing of the master clock pulse.
A signal provided by the memory circuit 28 which is a time division multiplexed signal of a right channel signal and a left channel signal is applied to D/A converters 29 and 30 so as to be separated to the right and left channels at a timing of the master clock pulse and converted to the original analog signals, i.e., audio signal.
A subcode detecting circuit 36 detects subcodes which are codes representing an address, the number of music, time required for performing the piece of music etc. from the signal which has been demodulated by the demodulation circuit 12 and supplies the detected subcodes to the system control circuit 37. The system control circuit 37 receives address, the number of music etc. designated by an operation key 38 through a decoder 39, compares them with the detected subcodes and drives the feed motor 8 through the feed motor driving circuit 40 so that they coincide with each other. The detected subcodes are indicated by a display unit 42 through a driving circuit 41.
In the control system described above, the prior art clock reproducing circuit 16 has been constructed as shown in FIG. 2. In FIG. 2, a clock detecting circuit 50 detects a clock signal from an output signal of the waveform shaping circuit 11. Since this clock signal is slightly irregular in its period, it is first converted by a frequency-voltage converter 51 into a voltage corresponding to its frequency and a voltage-controlled type oscillator (VCO) 52 is driven by this voltage to provide a clock signal of a regular period (about 1/n of the reproduced signal where n is an integer). However, if such irregularity of the clock signal from the waveform shaping circuit 11 is permissively slight, such clock detecting circuit 50 may be omitted and the output of the waveform shaping circuit 11 may be used as an input of the frequency-voltage converter 51. It should be noted here that as the VCO 52, a VCO which can oscillate for itself with a free-running frequency corresponding to such period may be used without preparing the detecting circuit 50 and the converter 51. A phase error detecting circuit 53 compares in phase the output of the waveform shaping circuit 11, i.e., the reproduced signal, with the output of the VCO 52 and controls the VCO 52 in such a manner that these outputs are brought in phase with each other. The VCO 52 thereby generates a reproduced clock signal synchronized with the reproduced signal.
FIG. 3 shows an example of a specific construction of the prior art phase error detecting circuit 53. In this circuit, the output of the waveform shaping circuit 11 is delayed by the output of the VCO 52. The output of the waveform shaping circuit 11 and a Q output of a D-flip-flop circuit 54 are applied to an exclusive OR gate 55. The output of the exclusive OR gate 55 is smoothed by a time constant circuit consisting of a resistor R1 and a capacitor C1 and the VCO 52 is controlled by the smoothed output of this time constant circuit.
FIGS. 4(a) through 4(e) are waveform diagrams respectively showing waveforms appearing in portions designated by reference characters (a) through (e) in the circuit of FIG. 3. If it is assumed that a state designated by P5 is one in which the signal of (a) and that of (b) are synchronized with each other, the control for synchronization may be performed in such a manner that the signal of (e) will become zero. According to this method, however, the phase error between the signals of (a) and (b) is corrected by a control in which the phase of the signal of (e) is shifted always in the direction of advancing the phase and never in the direction of delaying the phase. Consequently, though the phase error is decreased from P1 through P2, P3 and P4 to the state P5 in which the signals of (a) and (b) are synchronized, a slight excessive advancement in the phase causes a delay in the signal of (b) by one period as illustrated as a state P6 and the signal of (e) becomes large again. This necessitates the control to advance the phase of the signal of (b) from the initial state again and, accordingly, it is difficult to reach a stable state in which the signals of (a) and (b) are synchronized with each other.
If it is assumed that a state designated by P2 is one in which the signals of (a) and (b) are synchronized with each other, a control may be effected in such a manner that the voltage of the signal of (e) at the state P2 is made a reference voltage and the phase of the signal in (b) is advanced if the voltage of the signal of (e) is larger than this reference voltage whereas the phase is delayed if the voltage of the signal of (e) is smaller than the reference voltage. Since, however, the voltage of the signal of (e) is one derived by smoothing the signal of (d), the voltage of the signal of (e) varies depending upon frequency of generation of the signal of (d), i.e., frequency of inversion of the reproduced signal so that the coincidence of the voltage of the signal of (e) with the above described reference voltage does not necessarily represent a state in which the signals of (a) and (b) are synchronized with each other.